P-complete

Planar Circuit Value Problem (PCVP)

Input

An encoding $\overline{\alpha}$ of a planar Boolean circuit $\alpha$, inputs $x_1, \ldots, x_n$ and designated output $y$.

Problem

Is output $y$ of $\alpha$ true on inputs $x_1, \ldots, x_n$?

Definitions

See CVP. A planar circuit is one whose graph can be drawn in the plane with no edges crossing.

Status

$\P$-complete under $\NC^1$ reductions (Goldschlager [1]).

Remarks

The reduction to show hardness is from CVP and it’s done via a planar cross-over circuit using planar XOR circuits. Monotone planar cross-over circuits do not exist, and in fact the monotone version of PCVP is in $\mathsf{LOGCFL} \subseteq \NC^2$ when all inputs appear on one face of the planar embedding (Dymond and Cook [2][3], Goldschlager [4], Mayr [5]). The more general problem where inputs may appear anywhere is also in $\NC$ (Delcher and Kosaraju [6], Kosaraju [7]). A complete characterization of all bases from which it is possible to construct planar cross-over circuits is given in McColl [8].

References

  1. L. M. Goldschlager (1977). The monotone and planar circuit value problems are log space complete for P.
  2. P. W. Dymond and S. A. Cook (1980). Hardware complexity and parallel computation.
  3. P. W. Dymond and S. A. Cook (1989). Complexity theory of parallel time and hardware.
  4. L. M. Goldschlager (1980). A space efficient algorithm for the monotone planar circuit value problem.
  5. E. W. Mayr (1988). The dynamic tree expression problem.
  6. A. L. Delcher and S. R. Kosaraju (1991). An NC algorithm for evaluating monotone planar circuits.
  7. S. R. Kosaraju (1990). On the parallel evaluation of classes of circuits.
  8. W. F. McColl. Planar crossovers (1981). IEEE Transactions on Computers, C-30(3):223–225, 1981..
  9. Greenlaw, R., Hoover, H. J., and Ruzzo, W. L. (1995). Limits to Parallel Computation: P-Completeness Theory. Oxford University Press. Problem A.1.7.